The present invention generally relates to a communication system for establishing communications among a plurality of electronic appliances connected to each other via a communication control bus such as a serial bus standardized by, for instance, IEEE-1394 (will be referred to as an "IEEE1394 serial bus" hereinafter) capable of transmitting control signals and information signals in a mixed form. More specifically, the present invention is directed to a technique capable of assuring data read/write operations when data is read/written from/into a memory contained in a recording medium employed in one electronic appliance by another electronic appliance via the communication control bus.
Various communication systems have been proposed in the field, in which a plurality of electronic appliances are connected to each other via a communication control bus such as the IEEE1394 serial bus capable of transmitting control signals and information signals in the mixed manner, and the control signals and the information signals are communicated among these electronic appliances.
In FIG. 1, there is shown an example of such a communication system. This communication system is equipped with a first video tape recorder (will be referred to as a "VTR" hereinafter) 11, a second video tape recorder (VTR) 12, and a first camera-built-in type VTR (will be referred to as a "CAM" hereinafter) 13. Then, the first VTR 11 is connected to the second VTR 12 via a twisted pair cable 14, and the first VTR 11 is connected to the first CAM 13 via another twisted pair cable 15. These twisted pair cables 14 and 15 constitute the IEEE1394 serial bus.
As represented in FIG. 2, the signal transmissions among these plural electronic appliances are carried out by way of the time divisional multiplexing system in a preselected communication cycle (for instance 125 .mu.sec) in this communication system. The signal transmission is commenced in such a manner that an electronic appliance called as a "cycle master" sends out a cycle start packet indicative of the starting time of the communication cycle via the bus. It should be noted that a "cycle master" is automatically determined based on the procedure ruled in IEEE-1394 when the respective electronic appliances are connected to each other via an IEEE1394 serial bus cable.
There are two communication modes within 1 communication cycle, namely an I.sub.SO communication mode and an Async communication mode. In the I.sub.SO communication mode, an information signal such as video data and audio data is transmitted in an isochronous manner. In the Async communication mode, a control signal such as a connection control command is transmitted in an asynchronous manner. Then, an I.sub.so packet is transmitted prior to an Async packet. A plurality of I.sub.so data are discriminatable from each other by attaching channel numbers 1, 2, 3, . . . , N to the respective I.sub.so packets. A time period defined after a transmission of an I.sub.so packet is accomplished and until the next cycle start packet appears is used to transmit an Async packet.
When a video signal and an audio signal (will be referred to as an "audio/video signal" hereinafter) recorded on a video tape cassette are dubbing-processed via an IEEE1394 serial bus in the above-described communication system, the following case will now be considered. That is, as illustrated in FIG. 3, an audio/video signal recorded on a video tape cassette 21 loaded on the first CAM 13 is dubbing-processed to a video tape cassette 23 loaded on the first VTR 1.
In this case, a memory 22 and a memory 24 are assembled into package of these video tape cassettes 21 and 23 respectively. A memory assembled in package of a video tape cassette will be referred to an "MIC (Memory In Cassette)" hereinafter. The content information (data, title etc) of the audio/video signals recorded on the video tape cassettes 21 and 23 are readable/writable from/in these MICs 22 and 24.
It is assumed that when the audio/video signal recorded on the video tape cassette 21 is dubbing-processed to the video tape cassette 23, the content information stored in the MIC 22 is written into the MIC 24. At this time, the audio/video signal is transmitted via the bus as I.sub.so data shown in FIG. 2. On the other hand, the content information of the MIC 22 is transmitted via the bus as Async data.
Now, as represented in FIG. 4, in such a case that while the first VTR 11 reads therein the data stored in the MIC 22 by subdividing this data, the second VTR 12 rewrites the data (for instance, title) stored in the MIC 21, there is a certain possibility that the data which has been read before this title is rewritten can no longer constitute the correct information.